Microelectronic device designers often desire to increase the level of integration or density of features within a given semiconductor device architecture by reducing the critical dimensions of the individual features and by reducing the separation distance, or pitch, between neighboring features. In addition, microelectronic device designers often seek to design architectures that are not only compact, but also offer performance advantages, as well as simplified designs.
One example of a microelectronic device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many species of memory including, but not limited to, random-access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), FLASH memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (ReRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin-torque-transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.
A memory device may include an active surface including interacting components, such as transistors, capacitors, electrodes, diodes, other access devices, or other elements. During fabrication of the memory device, electrical connections may be formed between the active surface of the memory device and other portions thereof to form electrical connections to circuitry located away from the active surface.
For example, a typical memory cell of a memory device includes an access device (e.g. a transistor) and a memory storage structure (e.g., a capacitor) electrically coupled to the access device through a conductive contact. The access device generally includes a channel region between a pair of source/drain regions, and a gate electrode configured to electrically connect the source/drain regions to one another through the channel region. One or more of the source region, the drain region, and the gate electrode may be in electrical communication with one or more sources of electrical potential to operate the memory cell.
As the number of memory cells in a memory device increases, electrically connecting the memory cells to control logic circuitry and other components of the memory device can create feature sizing and spacing complications associated with the increased quantities and dimensions of routing and interconnect structures required to facilitate the electrical connection. Moreover, as the feature size of memory devices continues to shrink, it is more and more difficult to form patterns of features having a desired critical dimension. As the critical dimensions of the components of the memory device shrink, forming reliable electrical connections between electrically conductive components of the memory device becomes increasingly difficult.